HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learning by Anirban Sengupta, Rahul Chaurasia, Mahendra Rathor

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VHDL Implementation of Hybrid Block Cipher Method (SRC) by Ashwaq T. Hishem, Najwa M. Hassen, Ekhlas M. Farhan

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DESIGN AND ANALYSIS OF LOW POWER MULTIPLY AND ACCUMULATE UNIT USING PIXEL PROPERTIES REUSABILITY TECHNIQUE FOR IMAGE PROCESSING SYSTEMS by M. Madheswaran, S. Saravanan

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New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1} by Ahmad Hiasat

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A low cost advance encryption standard (AES) co-processor implementation by Orlando J. Hernandez, Thomas Sodon, Michael Adel, Nathan Kupp

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FPGA Implementation of Mean – Max Membership basedDefuzzifier Unit by Asim M. Murshid

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VLSI Implementation of Fully Parallel LTE Turbo Decoders by An Li, Luping Xiang, Taihai Chen, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo

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Analysis of Redundancy Techniques for Electronics Design—Case Study of Digital Image Processing by Padmanabhan Balasubramanian

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Hybrid genetic‐paired‐permutation algorithm for improved VLSI placement by Vladimir V. Ignatyev, Andrey V. Kovalev, Oleg B. Spiridonov, Viktor M. Kureychik, Alexandra S. Ignatyeva, Irina B. Safronenkova

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Review on VLSI design using optimization and self-adaptive particle swarm optimization by S.B. Vinay Kumar, P.V. Rao, H.A. Sharath, B.M. Sachin, U.S. Ravi, B.V. Monica

Subjects: “…VLSI design…”
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Gamification for Teaching Integrated Circuit Processing in an Introductory VLSI Design Course by Ángel Diéguez, Joan Canals, Sergio Moreno, Anna Vilà

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Test Generation Guided Design for Testability by Wu, Peng

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Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology by Abbas Asadi Aghbolaghi, Mehran Emadi

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Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions by Byeonggil Park, Jongsun Park, Youngjoo Lee

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An Efficient LUT Design on FPGA for Memory-Based Multiplication by C. S. Vinitha, R. K. Sharma

Subjects: “…vlsi design…”
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Efficient programmable power‐of‐two scaler for the three‐moduli set {2 by MohammadReza Taheri, Keivan Navi, Amir Sabbagh Molahosseini

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Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks by Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Carlos J. Jiménez-Fernández, Antonio J. Acosta, Ricardo Chaves

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Pipelined Two-Operand Modular Adders by M. Czyzak, J. Horiszny, R. Smyk

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A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems by Minjoon Kim

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Analysis of redundancy techniques for electronics design—case study of digital image processing by Balasubramanian, Padmanabhan

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