Evaluating Kernels on Xeon Phi to accelerate Gysela application by Latu Guillaume, Haefele Matthieu, Bigot Julien, Grandgirard Virginie, Cartier-Michaud Thomas, Rozar Fabien

“…This work describes the challenges presented by porting parts of the Gysela code to the Intel Xeon Phi coprocessor, as well as techniques used for optimization, vectorization and tuning that can be applied to other applications. …”
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Improving main memory hash joins on Intel Xeon Phi processors by Jha, Saurabh, He, Bingsheng, Lu, Mian, Cheng, Xuntao, Huynh, Huynh Phung

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MPI communication benchmarking on Intel Xeon dual quad-core processor cluster by Ismail, Roswan, Abdul Hamid, Nor Asilah Wati, Othman, Mohamed, Latip, Rohaya, Sanwani, Mohd Azizi

“…This paper reports the measurements of MPI communication benchmarking on Khaldun cluster which ran on Linux-based IBM Blade HS21 Servers with Intel Xeon dual quad-core processor and Gigabit Ethernet interconnect. …”
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Evaluating New Architectural Features Of The Intel(R) Xeon(R) 7500 Processor For Hpc Workloads by Paweł Gepner, David Fraser, Michał Kowalik, Kazimierz Waćkowski

“…We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolutionof 16 node clusters based on these CPUs. …”
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Evaluation of the Intel Xeon Phi 7120 and NVIDIA K80 as accelerators for two-dimensional panel codes. by Lukas Einkemmer

“…In this paper we evaluate the performance of such an optimization algorithm on modern accelerators (more specifically, the Intel Xeon Phi 7120 and the NVIDIA K80). For that purpose, we have implemented an optimized version of the algorithm on the CPU and Xeon Phi (based on OpenMP, vectorization, and the Intel MKL library) and on the GPU (based on CUDA and the MAGMA library). …”
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Correction: Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP

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Correction: Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. by Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Víctor Viñals-Yúfera

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Many-core needs fine-grained scheduling : a case study of query processing on Intel Xeon Phi processors by Cheng, Xuntao, He, Bingsheng, Lu, Mian, Lau, Chiew Tong

“…Emerging many-core processors feature very high memory bandwidth and computational power. For example, Intel Xeon Phi many-core processors of the Knights Corner (KNC) and Knights Landing (KNL) architectures embrace 60 to 64 x86-based CPU cores with 512-bit SIMD capabilities and high-bandwidth memories like the GDDR5 on KNC and on-package DRAMs on KNL. …”
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Performance analysis of Message Passing Interface collective communication on intel xeon quad-core gigabit ethernet and infiniband clusters by Ismail, Roswan, Abdul Hamid, Nor Asilah Wati, Othman, Mohamed, Latip, Rohaya

“…Consequently, this study concentrates on benchmarking MPI implementation on multi-core architecture by measuring the performance of Open MPI collective communication on Intel Xeon dual quad-core Gigabit Ethernet and InfiniBand clusters using SKaMPI. …”
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Performance Evaluation of Massively Parallel Systems Using SPEC OMP Suite by Dheya Mustafa

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A Comparative Study of Methods for Measurement of Energy of Computing by Muhammad Fahad, Arsalan Shahid, Ravi Reddy Manumachu, Alexey Lastovetsky

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Plasma Physics by Brown, S. C., Arunasalam, V., Hooper, E. B., Jr., Jameson, P. W., Coccoli, J. D.

Subjects: “…Anomalous Pulsed Emission and Absorption by a Xeon Plasma at the Electron-Cyclotron Frequency…”
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Software prefetching for unstructured mesh applications by Hadade, I, Jones, T, Wang, F, Di Mare, L

“…Through this, we show significant full application speed-ups on a range of processors and realistic test cases in both single core/tile and full socket configurations, such as 1.14× on the Intel Xeon Sandy Bridge, 1.09× on the Intel Xeon Broadwell, 1.29× on the Intel Xeon Skylake, 1.99× on the in-order Intel Xeon Phi Knights Corner coprocessor, and 1.51× on the out-of-order Intel Xeon Phi Knights Landing many-core processor.…”

Vectorizing unstructured mesh computations for many-core architectures by Giles, M, Mudalige, G

“…This paper presents results on achieving high performance through vectorization on CPUs and the Xeon-Phi on a key class of irregular applications: unstructured mesh computations. …”

Some useful optimisations for unstructured computational fluid dynamics codes on multicore and manycore architectures by Hadade, I, Wang, F, Carnevale, M, Di Mare, L

“…This paper presents a number of optimisations for improving the performance of unstructured computational fluid dynamics codes on multicore and manycore architectures such as the Intel Sandy Bridge, Broadwell and Skylake CPUs and the Intel Xeon Phi Knights Corner and Knights Landing manycore processors. …”

The VOLNA-OP2 tsunami code (version 1.5) by Reguly, I, Giles, D, Gopinathan, D, Quivy, L, Beck, J, Giles, M, Guillas, S, Dias, F

“…The scalability of the code is demonstrated on three supercomputers, built with classical Xeon CPUs, the Intel Xeon Phi, and NVIDIA P100 GPUs. …”

A polyphase filter for many-core architectures by Adámek, K, Novotný, J, Armour, W

“…We describe in detail our implementation of the polyphase filter algorithm and its behaviour on three generations of NVIDIA GPU cards (Fermi, Kepler, Maxwell), on the Intel Xeon CPU and Xeon Phi (Knights Corner) platforms. …”

Modern multicore and manycore architectures: Modelling, optimisation and benchmarking a multiblock CFD code by Hadade, I, Di Mare, L

“…We report significant speedups for single thread execution across both kernels: 2-5X on the multicore CPUs and 14-23X on the Xeon Phi coprocessor. Computations at full node and chip concurrency deliver a factor of three speedup on the multicore processors and up to 24X on the Xeon Phi manycore coprocessor.…”

Energy Efficiency of a New Parallel PIC Code for Numerical Simulation of Plasma Dynamics in Open Trap by Igor Chernykh, Igor Kulikov, Vitaly Vshivkov, Ekaterina Genrikh, Dmitry Weins, Galina Dudnikova, Ivan Chernoshtanov, Marina Boronina

“…This code can be auto-vectorized by the Fortran compiler for Intel Xeon processors with AVX-512 instructions such as Intel Xeon Phi and the highest series of all generations of Intel Xeon Scalable processors. …”
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NOHOST : a new storage architecture for distributed storage systems by Chung, Chanwoo (Computer scientist) Massachusetts Institute of Technology

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