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321
8-bit CMOS asynchronous dynamic reference ADC
Published 2024“…In a SAR ADC, the output bits will be resolve in a successive matter by its previous output as the name suggested.…”
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Final Year Project (FYP) -
322
Characterization of 12-bit SAR ADC for wireless applications
Published 2018“…The dissertation aims to meet the specification values for a 12 bit SAR ADC in all specified supply voltages and temperatures. …”
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Thesis -
323
Design a 16-bit Low power multiplier
Published 2018“…This project is aiming to use HDL and Synopsys IC design tools to design a 16-bit Low Power Multiplier. We will have two designs, one is a dynamic 16-Bit Braun Multiplier and the other is a 16-bit Sequential Multiplier. …”
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Final Year Project (FYP) -
324
Design of 128-Bit asynchronous-logic AES processor
Published 2019“…This project establishes a methodology to design a 128-Bit Asynchronous-Logic AES processor, allowing for quicker simulation and benchmarking of different Asynchronous designs. …”
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Final Year Project (FYP) -
325
Event-triggered feedback control with one-bit transmission
Published 2019Get full text
Final Year Project (FYP) -
326
On 3-share threshold implementations for 4-Bit S-boxes
Published 2013Get full text
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Conference Paper -
327
Design of a low bit rate STDM multiplexing
Published 2011“…A low bit rate STDM multiplexer architecture design for thing route channels is provided in this chapter. …”
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Book Chapter -
328
Functional Pearl: Perfect trees and bit−reversal permutations
Published 2000“…An efficient iterative version of the FFT algorithm performs as a first step a bit-reversal permutation of the input list. The bit-reversal permutation swaps elements whose indices have binary representations that are the reverse of each other. …”
Journal article -
329
Random bit quadrature and approximation of distributions on Hilbert Spaces
Published 2018“…We consider restricted Monte Carlo algorithms, which may only use random bits instead of random numbers. We determine the asymptotics (in some cases sharp up to multiplicative constants, in the other cases sharp up to logarithmic factors) of the corresponding n-th minimal error in terms of the decay of the eigenvalues of the covariance operator of X. …”
Journal article -
330
Random bit multilevel algorithms for stochastic differential equations
Published 2019“…We construct a random bit multilevel Euler algorithm and establish upper bounds for its error and cost. …”
Journal article -
331
Building better bit-blasting for floating-point problems
Published 2019“…An effective approach to handling the theory of floating-point is to reduce it to the theory of bit-vectors. Implementing the required encodings is complex, error prone and requires a deep understanding of floating-point hardware. …”
Conference item -
332
Guaranteed energy-efficient bit reset in finite time.
Published 2014“…Landauer's principle states that it costs at least kBTln2 of work to reset one bit in the presence of a heat bath at temperature T. …”
Journal article -
333
Formal verification of bit-vector invertibility conditions in Coq
Published 2023“…We prove the correctness of invertibility conditions for the theory of fixed-width bit-vectors—used to solve quantified bit-vector formulas in the Satisfiability Modulo Theories (SMT) solver cvc5— in the Coq proof assistant. …”
Conference item -
334
Design of 8-Bit CMOS Digital to Analog Converter
Published 2001“…The modules include thermometer decoder, latch, 5-bit LSB inverted R-2R ladder, 3-bit MSB current source, two-way CMOS current switch and the current to voltage converter. …”
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Thesis -
335
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336
A Comparative statistical analysis of pseudorandom bit sequences
Published 2009“…In this paper, we examined two kinds of pseudorandom bit sequence (PRBS); conventional PRBS and chaos-based PRBS. …”
Conference or Workshop Item -
337
Bit inverting map method for improved steganography scheme
Published 2016“…This study proposes an improved Bit Inverting Map (BIM) method and a new scheme for embedding secret message into an image. …”
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Thesis -
338
Multi-core 16-bit CPUs for PLC processor
Published 2022“…For more than a single bit input or data processing, a general purpose CPU is needed to save resources. …”
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Thesis -
339
A bit-serial architecture for a multiplierless DCT
Published 2003“…For low power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. …”
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Article -
340