8-bit CMOS asynchronous dynamic reference ADC by Ng, Xiang Yang

“…In a SAR ADC, the output bits will be resolve in a successive matter by its previous output as the name suggested.…”
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Characterization of 12-bit SAR ADC for wireless applications by Bhagyalakshmi Manjunatha

“…The dissertation aims to meet the specification values for a 12 bit SAR ADC in all specified supply voltages and temperatures. …”
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Design a 16-bit Low power multiplier by Gu, Bin

“…This project is aiming to use HDL and Synopsys IC design tools to design a 16-bit Low Power Multiplier. We will have two designs, one is a dynamic 16-Bit Braun Multiplier and the other is a 16-bit Sequential Multiplier. …”
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Design of 128-Bit asynchronous-logic AES processor by Chua, Elton Yi Wei

“…This project establishes a methodology to design a 128-Bit Asynchronous-Logic AES processor, allowing for quicker simulation and benchmarking of different Asynchronous designs. …”
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Event-triggered feedback control with one-bit transmission by Muhammad Mirza Zulkifli

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On 3-share threshold implementations for 4-Bit S-boxes by Kutzner, Sebastian, Nguyen, Phuong Ha, Poschmann, Axel, Wang, Huaxiong

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Design of a low bit rate STDM multiplexing by Shah, Asadullah, Abdullah Zammarh, Nuha

“…A low bit rate STDM multiplexer architecture design for thing route channels is provided in this chapter. …”
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Functional Pearl: Perfect trees and bit−reversal permutations by Hinze, R

“…An efficient iterative version of the FFT algorithm performs as a first step a bit-reversal permutation of the input list. The bit-reversal permutation swaps elements whose indices have binary representations that are the reverse of each other. …”

Random bit quadrature and approximation of distributions on Hilbert Spaces by Giles, M, Hefter, M, Mayer, L, Ritter, K

“…We consider restricted Monte Carlo algorithms, which may only use random bits instead of random numbers. We determine the asymptotics (in some cases sharp up to multiplicative constants, in the other cases sharp up to logarithmic factors) of the corresponding n-th minimal error in terms of the decay of the eigenvalues of the covariance operator of X. …”

Random bit multilevel algorithms for stochastic differential equations by Giles, MB, Hefter, M, Mayer, L, Ritter, K

“…We construct a random bit multilevel Euler algorithm and establish upper bounds for its error and cost. …”

Building better bit-blasting for floating-point problems by Brain, M, Schanda, F, Sun, Y

“…An effective approach to handling the theory of floating-point is to reduce it to the theory of bit-vectors. Implementing the required encodings is complex, error prone and requires a deep understanding of floating-point hardware. …”

Guaranteed energy-efficient bit reset in finite time. by Browne, C, Garner, A, Dahlsten, O, Vedral, V

“…Landauer's principle states that it costs at least kBTln2 of work to reset one bit in the presence of a heat bath at temperature T. …”

Formal verification of bit-vector invertibility conditions in Coq by Ekici, B, Viswanathan, A, Zohar, Y, Tinelli, C, Barrett, C

“…We prove the correctness of invertibility conditions for the theory of fixed-width bit-vectors—used to solve quantified bit-vector formulas in the Satisfiability Modulo Theories (SMT) solver cvc5— in the Coq proof assistant. …”

Design of 8-Bit CMOS Digital to Analog Converter by Tan, Gim Heng

“…The modules include thermometer decoder, latch, 5-bit LSB inverted R-2R ladder, 3-bit MSB current source, two-way CMOS current switch and the current to voltage converter. …”
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Arithmetic logic unit (ALU) - bit slice approach. by Suparjo, Bambang Sunaryo, Mansor, Mohd Isa

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A Comparative statistical analysis of pseudorandom bit sequences by Kadir, Rashidah, Maarof, Mohd. Aizaini

“…In this paper, we examined two kinds of pseudorandom bit sequence (PRBS); conventional PRBS and chaos-based PRBS. …”

Bit inverting map method for improved steganography scheme by Fadhil, Ammar Mohammedali

“…This study proposes an improved Bit Inverting Map (BIM) method and a new scheme for embedding secret message into an image. …”
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Multi-core 16-bit CPUs for PLC processor by Gan, Chi Qian

“…For more than a single bit input or data processing, a general purpose CPU is needed to save resources. …”
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A bit-serial architecture for a multiplierless DCT by Choomchuay, S., Timakul, S.

“…For low power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. …”
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Performance comparison between flat antenna and parabolic dish offset antenna based on bit error rate (Bit Error Rate) [electronic resource] / by 447861 Quee, Tah Chuan, Fakulti Kejuruteraan Elektrik