Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine by Sinangil, Mahmut E., Chandrakasan, Anantha P., Sze, Vivienne, Zhou, Minhua, Sinangil, Mahmut

“…Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes.…”
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Experiments in dynamic control of autonomous marine vehicles using acoustic modems by Gilbertson, Eric W., Leighton, Joshua C., Cheung, Mei Yi, Hover, Franz S., Reed, Brooks

“…Packet loss occurs widely, bit rates are low, and there are significant delays. …”
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A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications by Mercier, Patrick Philip, Bandyopadhyay, Saurav, Lysaght, Andrew Christopher, Stankovic, Konstantina M., Chandrakasan, Anantha P.

“…Supporting both OOK and FSK modulations at 2.4 GHz, the transmitter consumed as low as 38 pJ/bit at an active-mode data rate of 5 Mbps. The loop antenna and integrated diodes were also used as part of a wireless power transfer receiver in order to kick-start the system power supply prior to energy harvesting operation.…”
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AdaptCast: An integrated source to transmission scheme for wireless sensor networks by Angelopoulos, Georgios, Medard, Muriel, Chandrakasan, Anantha P.

“…The proposed scheme does not suffer from the sudden degradation in the tradeoff between distortion and SNR of rated channel coding schemes due to its direct, relative bit importance preserving modulation mapping. In addition, it does not require continuous feedback or channel state information (CSI) as a result of its rateless operation. …”
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A 5-Gb/s automatic gain control amplifier with temperature compensation by Liu, Chang, Yan, Yuepeng, Goh, Wang Ling, Xiong, Yong-Zhong, Zhang, Lijun, Madihian, Mohammad

“…With a 215 - 1 pseudo-random bit sequence at 5-Gb/s, the measured peak-to-peak jitter is less than 40pspp across the -20°C-200°C temperature range. …”
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Nyquist WDM superchannel using offset-16QAM and receiver-side digital spectral shaping by Xiang, Meng, Fu, Songnian, Tang, Ming, Tang, Haoyuan, Shum, Perry, Liu, Deming

“…Here, we propose and numerically investigate a Nyquist WDM superchannel using offset-16QAM and receiver-side digital spectral shaping (RS-DSS), achieving a spectral efficiency up to 7.44 bit/s/Hz with 7% hard-decision forward error correction (HD-FEC) overhead. …”
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Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1} by Tay, Thian Fatt, Chang, Chip-Hong, Low, Jeremy Yung Shern

“…A complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. …”
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Single-event-transient resilient memory for DSP in space applications by Lwin, Ne Kyaw Zwa, Sivaramakrishnan, H., Chong, Kwen-Siong, Lin, Tong, Shu, Wei, Chang, Joseph S.

“…Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells.…”
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A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory by Chun, Ki Chul, Zhao, Hui, Harms, Jonathan D., Kim, Tony Tae-Hyoung, Wang, Jian-Ping, Kim, Chris H.

“…We focus on the read and write performances of a STT-MRAM based cache rather than the obvious advantages such as the denser bit-cell and zero static power. An accurate MTJ macromodel capturing key MTJ properties was adopted for efficient Monte Carlo simulations. …”
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A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS by Balachandran, Arya, Chen, Yong, Boon, Chirn Chye

“…The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. …”
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Urban sound analysis and synthesis using artificial intelligence by Guo, Zixun

“…Digital sound also has its unique sets of features such as sampling frequency, bit depth. Various research work has also utilized sound features in the frequency domain such as bandwidth. …”
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Multi-carrier M-ary DCSK system with code index modulation : an efficient solution for chaotic communications by Cai, Guofa, Fang, Yi, Wen, Jinming, Mumtaz, Shahid, Song, Yang, Frascolla, Valerio

“…With an aim to making full use of the system energy resources, the reference signals in all subcarriers are coded by a Walsh code to carry additional information bits. The analytical bit-error-rate (BER) expressions of the proposed CIMMC-M-DCSK system are derived over additive white Gaussian noise (AWGN) as well as multipath Rayleigh fading channels. …”
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Blind reconstruction of Reed-Solomon encoder and interleavers over noisy environment by Swaminathan, Ramabadran, Madhukumar, A. S., Wang, Guohua, Ting, Shang Kee

“…In addition, synchronization compensation through appropriate bit/symbol positioning is integrated with the proposed code and interleaver parameter estimation algorithms. …”
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Practical side-channel based model extraction attack on tree-based machine learning algorithm by Jap, Dirmanto, Yli-Mäyry, Ville, Ito, Akira, Ueno, Rei, Bhasin, Shivam, Homma, Naofumi

“…It has been shown in a recent publication, that Bonsai, a small tree-based algorithm, can be successfully fitted in a small 8-bit microcontroller. However, the security of machine learning algorithm has also been a major concern, especially with the threat of secret parameter recovery which could lead to breach of privacy. …”
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Simulation of resistive random-access memory (RRAM) : SPICE modelling of RRAM device by Lian, Jie

“…RRAM is considered a promising candidate for next-generation memory due to its non-volatile property, simple structure, high density, low power consumption, fast speed, multi-bit storage, and CMOS process capability. This dissertation will first review some basic concepts about RRAM and operation principles, conduction mechanisms, and typical materials and structures. …”
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Nonvolatile multistates memories for high-density data storage by Cao, Qiang, Lü, Weiming, Wang, Renshaw Xiao, Guan, Xinwei, Wang, Lan, Yan, Shishen, Wu, Tom, Wang, Xiaolin

“…Owing to the capability to store data in more than a single bit (0 or 1), the storage density is dramatically enhanced without scaling down the memory cell, making memory devices more efficient and less expensive. …”
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On evaluating fault resilient encoding schemes in software by Breier, Jakub, Hou, Xiaolu, Liu, Yang

“…Based on these findings, we develop evaluation metric that can be used universally to determine the robustness of a software encoding scheme against bit flip faults and instruction skips. We provide a way to select a code according to user criteria and also a dynamic code analysis method to estimate the level of protection of assembly implementations using encoding schemes. …”
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A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS by Palaniappan, Arjun Ramaswami, Siek, Liter

“…The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. …”
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Advanced 3D integration technologies in various quantum computing devices by Zhao, Peng, Lim, Yu Dian, Li, Hong Yu, Guidoni, Luca, Tan, Chuan Seng

“…In this review, we focus on four popular quantum bit (qubit) candidates (trapped ion, superconducting circuit, silicon spin and photon) which are encoded by distinct physical systems but all intrinsically compatible with advanced CMOS fabrication process. …”
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Tight bounds for the subspace sketch problem with applications by Li, Yi, Wang, Ruosong, Woodruff, David P.

“…We show if p ≥ 0 is not a positive even integer and d = Ω (log(1/∊ )), then Ω (∊-2d) bits are necessary. On the other hand, if p is a positive even integer, then there is an upper bound of O(dp log(nd)) bits independent of \varepsilon. …”
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