An Ultracompact Single‐Ferroelectric Field‐Effect Transistor Binary and Multibit Associative Search Engine por Xunzhao Yin, Franz Müller, Qingrong Huang, Chao Li, Mohsen Imani, Zeyu Yang, Jiahao Cai, Maximilian Lederer, Ricardo Olivo, Nellie Laleni, Shan Deng, Zijian Zhao, Zhiguo Shi, Yiyu Shi, Cheng Zhuo, Thomas Kämpfe, Kai Ni

Materias: Enlace del recurso

Approximation-Aware Training for Efficient Neural Network Inference on MRAM Based CiM Architecture por Hemkant Nehete, Sandeep Soni, Tharun Kumar Reddy Bollu, Balasubramanian Raman, Brajesh Kumar Kaushik

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Straightforward data transfer in a blockwise dataflow for an analog RRAM-based CIM system por Yuyi Liu, Bin Gao, Peng Yao, Qi Liu, Qingtian Zhang, Dong Wu, Jianshi Tang, He Qian, Huaqiang Wu

Materias: “…computation-in-memory…”
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Area Efficient Computing-in-Memory Architecture Using STT/SOT Hybrid Three Level Cell por Seema Dhull, Arshid Nisar, Rakesh Bhat, Brajesh Kumar Kaushik

Materias: “…Compute-in-memory…”
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In‐Memory Binary Vector–Matrix Multiplication Based on Complementary Resistive Switches por Tobias Ziegler, Rainer Waser, Dirk J. Wouters, Stephan Menzel

Materias: Enlace del recurso

Recovering accuracy of RRAM-based CIM for binarized neural network via Chip-in-the-loop training por Chong, Yi Sheng, Goh, Wang Ling, Ong, Yew Soon, Nambiar, Vishnu P., Do, Anh Tuan

Materias: Enlace del recurso

Recent Progress of Non-Volatile Memory Devices Based on Two-Dimensional Materials por Jiong Pan, Zeda Wang, Bingchen Zhao, Jiaju Yin, Pengwen Guo, Yi Yang, Tian-Ling Ren

Materias: Enlace del recurso

SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology por Rajiv V. Joshi, J. Frougier, Alberto Cestero, Crystal Castellanos, Sudipto Chakraborty, Carl Radens, M. Silvestre, S. Lucarini, I. Ahsan, E. Leobandung

Materias: “…Compute-in-memory (CIM)…”
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Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator por Wonbo Shim, Shimeng Yu

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CRUS: A Hardware-Efficient Algorithm Mitigating Highly Nonlinear Weight Update in CIM Crossbar Arrays for Artificial Neural Networks por Junmo Lee, Joon Hwang, Youngwoon Cho, Min-Kyu Park, Woo Young Choi, Sangbum Kim, Jong-Ho Lee

Materias: Enlace del recurso

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators por Ziyu Wang, Yuting Wu, Yongmo Park, Sangmin Yoo, Xinxin Wang, Jason K. Eshraghian, Wei D. Lu

Materias: “…compute-in-memory…”
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Hardware for Deep Learning Acceleration por Choongseok Song, ChangMin Ye, Yonguk Sim, Doo Seok Jeong

Materias: “…compute‐in‐memory…”
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IGZO CIM: Enabling In-Memory Computations Using Multilevel Capacitorless Indium–Gallium–Zinc–Oxide-Based Embedded DRAM Technology por Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni

Materias: “…Compute-in-memory (CIM)…”
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Compute-in-Memory for Numerical Computations por Dongyan Zhao, Yubo Wang, Jin Shao, Yanning Chen, Zhiwang Guo, Cheng Pan, Guangzhi Dong, Min Zhou, Fengxia Wu, Wenhe Wang, Keji Zhou, Xiaoyong Xue

Materias: “…compute-in-memory (CIM)…”
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FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis por Waqas Gul, Maitham Shams, Dhamin Al-Khalili

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Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications por Chan-Gi Yook, Jung Nam Kim, Yoon Kim, Wonbo Shim

Materias: “…compute-in-memory (CIM)…”
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Memristive Devices for Time Domain Compute-in-Memory por Florian Freye, Jie Lou, Christopher Bengel, Stephan Menzel, Stefan Wiefels, Tobias Gemmeke

Materias: “…Compute-in-memory (CIM)…”
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Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter por Dong Suk Kang, Shimeng Yu

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Improving Linearity and Symmetry of Synaptic Update Characteristics and Retentivity of Synaptic States of the Domain-Wall Device Through Addition of Edge Notches por Raman Hissariya, Debanjan Bhowmik

Materias: “…Compute-in-memory (CIM) arrays…”
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Design and investigation of computation-in-memory based low power hybrid MTJ/CMOS logic gates por Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat

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