Showing 101 - 120 results of 617 for search '"formal verification"', query time: 0.37s Refine Results
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    End-to-end formal verification of a RISC-V processor extended with capability pointers by Gao, D, Melham, T

    Published 2021
    “…This case study presents the formal verification of CHERI-Flute, a modified version of Flute that implements CHERI-RISC-V, against the Sail CHERI-RISC-V specification. …”
    Conference item
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    Is Formal Verification of seL4 Adequate to Address the Key Security Challenges of Kernel Design? by Mina Soltani Siapoush, Jim Alves-Foss

    Published 2023-01-01
    “…Their continuous advances require formal verification that guarantees the accuracy of their functionalities. …”
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    Article
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    Formal Verification of Usage Control Models: A Case Study of UseCON Using TLA+ by Antonios Gouglidis, Christos Grompanopoulos, Anastasia Mavridou

    Published 2018-06-01
    “…However, these concepts may introduce an additional level of complexity to the underlying model, rendering its definition a cumbersome and prone to errors process. Applying a formal verification technique allows for a rigorous analysis of the interactions amongst the components, and thus for formal guarantees in respect of the correctness of a model. …”
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    Article
  15. 115

    Convolutional neural network designed as small truth tables, application to cryptography, formal verification & explainability by Benamira, Adrien

    Published 2024
    “…This thesis addresses three primary challenges: the absence of global and precise interpretability in DCNNs, the need for exact, comprehensive, sound, and efficient formal verification of DCNN properties, and the looming privacy threat to user input in cloud-based DCNN deployments for sensitive data. …”
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    Thesis-Doctor of Philosophy
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    Design and implementation of formal verification tool for combinational circuits using automatic test pattern generation by Tan, Sue Yee.

    Published 2010
    “…Therefore a design error could be detected using formal verification where simulation cannot detect. Therefore Formal Verification is a better choice to detect any error in the design. …”
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    Final Year Project (FYP)
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