Showing 1 - 8 results of 8 for search '"low thermal budget"', query time: 0.24s Refine Results
  1. 1
    High Gauge Factor Piezoresistors Using Aluminium Induced Crystallisation of Silicon at Low Thermal Budget

    High Gauge Factor Piezoresistors Using Aluminium Induced Crystallisation of Silicon at Low Thermal Budget by Ian Chuang, Aron Michael, Chee Yee Kwok

    Published 2017-09-01
    Subjects:
    Get full text
    Article
  2. 2
    Low‐Thermal‐Budget Doping of 2D Materials in Ambient Air Exemplified by Synthesis of Boron‐Doped Reduced Graphene Oxide

    Low‐Thermal‐Budget Doping of 2D Materials in Ambient Air Exemplified by Synthesis of Boron‐Doped Reduced Graphene Oxide by Jun‐Hwe Cha, Dong‐Ha Kim, Cheolmin Park, Seon‐Jin Choi, Ji‐Soo Jang, Sang Yoon Yang, Il‐Doo Kim, Sung‐Yool Choi

    Published 2020-04-01
    Subjects:
    Get full text
    Article
  3. 3
    Hard-Baked Photoresist as a Sacrificial Layer for Sub-180 °C Surface Micromachining Processes

    Hard-Baked Photoresist as a Sacrificial Layer for Sub-180 °C Surface Micromachining Processes by Hani H. Tawfik, Mohannad Y. Elsayed, Frederic Nabki, Mourad N. El-Gamal

    Published 2018-05-01
    Subjects:
    Get full text
    Article
  4. 4
    Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

    Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration by Shujuan Mao, Jianfeng Gao, Xiaobin He, Weibing Liu, Jinbiao Liu, Guilei Wang, Na Zhou, Yanna Luo, Lei Cao, Ran Zhang, Haochen Liu, Xun Li, Yongliang Li, Zhenhua Wu, Junfeng Li, Jun Luo, Chao Zhao, Wenwu Wang, Huaxiang Yin

    Published 2022-04-01
    Subjects:
    Get full text
    Article
  5. 5
    Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

    Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs by Catherine Langpoklakpam, An-Chen Liu, Neng-Jie You, Ming-Hsuan Kao, Wen-Hsien Huang, Chang-Hong Shen, Jerry Tzou, Hao-Chung Kuo, Jia-Min Shieh

    Published 2023-02-01
    Subjects: “…low thermal budget gate first process…”
    Get full text
    Article
  6. 6
    Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

    Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits by Tung-Ying Hsieh, Ping-Yi Hsieh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Meng-Chyi Wu

    Published 2020-07-01
    Subjects:
    Get full text
    Article
  7. 7
    Low‐Temperature Nanosecond Laser Process of HZO‐IGZO FeFETs toward Monolithic 3D System on Chip Integration

    Low‐Temperature Nanosecond Laser Process of HZO‐IGZO FeFETs toward Monolithic 3D System on Chip Integration by Dongsu Kim, Heejae Jeong, Goeun Pyo, Su Jin Heo, Seunghun Baik, Seonhyoung Kim, Hong Soo Choi, Hyuk‐Jun Kwon, Jae Eun Jang

    Published 2024-07-01
    Subjects:
    Get full text
    Article
  8. 8
    Temperature-modulated crystallographic orientation and electrical properties of BiFeO3 thick films sputtered on LaNiO3/Pt/Ti/SiO2/Si for piezo-MEMS applications

    Temperature-modulated crystallographic orientation and electrical properties of BiFeO3 thick films sputtered on LaNiO3/Pt/Ti/SiO2/Si for piezo-MEMS applications by Hongyu Luo, Miaomiao Niu, Hanfei Zhu, Li Li, Hongbo Cheng, Chao Liu, Jianting Li, Yuyao Zhao, Chenxi Zhang, Xiaojie Cao, Isaku Kanno, Qingguo Chi, Jun Ouyang

    Published 2024-12-01
    Subjects:
    Get full text
    Article

Search Tools: