A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure by Muhazam Mustapha, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, Bakhtiar Affendi Rosdi

“…As a solution, a method for realizing low transistor count XOR/XNOR gates using a special property of symmetric Boolean function is proposed. …”
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Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems by Zhou, Rong

“…Comparatively, the reported async QDI methodologies dissipate 617µW@50MHz (1.77× power dissipation as that of the proposed methodology), feature 9684 transistors (1.4× transistor count as that of the proposed methodology). …”
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A review of crosstalk polymorphic circuits and their scalability by Md Arif Iqbal, Srinivas Rahul Sapireddy, Sumanth Dasari, Kazi Asifuzzaman, Mostafizur Rahman

“…In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. …”
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Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier by R. Srivastava, M. Gupta, U. Singh

“…The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. …”
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A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) by Zhou, Rong, Chong, Kwen-Siong, Chang, Joseph Sylvester, Gwee, Bah Hwee

“…Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. …”
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High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits by Ho, Weng-Geng, Liu, Nan, Ne, Kyaw Zwa Lwin, Chong, Kwen-Siong, Gwee, Bah Hwee, Chang, Joseph Sylvester

“…Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. …”
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A full-custom IC design flow high speed design using 16-bit full adder by Teo, Kok Xuan.

“…Many designers try to reduce transistor count in attempt to improve performance such as speed and power consumption. …”
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Ternary Logics Based on 2D Ferroelectric-Incorporated 2D Semiconductor Field Effect Transistors by Guangchao Zhao, Xingli Wang, Xingli Wang, Weng Hou Yip, Nguyen To Vinh Huy, Philippe Coquet, Philippe Coquet, Mingqiang Huang, Beng Kang Tay, Beng Kang Tay

“…However, the excessive transistor count of ternary logic gates has impeded their industry applications for decades. …”
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Ternary logics based on 2D ferroelectric-incorporated 2D semiconductor field effect transistors by Zhao, Guangchao, Wang, Xingli, Yip, Weng Hou, Vinh Huy, Nguyen To, Coquet, Philippe, Huang, Mingqiang, Tay, Beng Kang

“…However, the excessive transistor count of ternary logic gates has impeded their industry applications for decades. …”
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Design and analysis of energy‐efficient compressors based on low‐power XOR gates in carbon nanotube technology by Elmira Tavakkoli, Mahdi Aminian

“…The proposed circuits are investigated in terms of process, voltage and temperature variations, delay, power dissipation, energy, power‐delay product (PDP) and transistor count. All the proposed and referenced designs are simulated using an HSPICE tool in a 32 nm CNTFET Stanford technology model. …”
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A full-custom IC design flow low power design using 16-bit full adder by Lim, Valerie Ying Fang.

“…Comparisons were made between two 16-bit full adders of the same transistor count, 28T CMOS complementary full adder and mirror full adder. …”
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Unified System Network Architecture: Flexible and Area-Efficient NoC Architecture with Multiple Ports and Cores by Phan-Duy Bui, Chanho Lee

“…In recent years, as semiconductor manufacturing processes have been steadily scaled down, the transistor count fabricated on a single silicon die can reach up to a billion units. …”
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CNTFET-based digital arithmetic circuit designs in ternary logic with improved performance by Namineni Gireesh, Shaik Javid Basha, Ahmed Elbarbary

“…The proposed THA and TMUL uses 41 and 33 CNTFETs and that resulting in a 54.44 % and 45 % reduction in transistor count, which plays major role for delay and power optimization. …”
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An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic by Shoba Mohan, Nakkeeran Rangaswamy

“…Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. …”
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Novel Low-Complexity and Low-Power Flip-Flop Design by Jin-Fa Lin, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, Shao-Wei Yu

“…These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). …”
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Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs by Meng-Chou Chang, Kai-Lun He, Yu-Chieh Wang

“…An independent-gate FinFET can operate in two modes: SG (shorted-gate) and IG (independent-gate) modes, and thus a FinFET-based circuit offers rich design options for lower power, better performance or reduced transistor count. In this paper, we present two novel dynamically power-gated FinFET TCAM cells, called DPG-17T and DPG-16T, which power-gate the prefix data storage unit when storing a ‘don't care’ value. …”
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Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors by Puvanaah Manokaran, Ahmad Anwar Zainuddin

“… The method of huge integrating involves implementing a significant transistor count in an extremely condensed space. Combinatorial logic has shown to be particularly effective in quantum computing as well as other designing applications. …”
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Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL by Belegehalli Siddaiah Premananda, Srivaths Sreedhar

“…A power reduction of up to 32% has been observed while keeping the transistor count to a minimum.…”
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Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect by Chiew , Chong Giap

“…The proposed design achieves a data rate of 2 Gbps small area 38.71 μm² with architectural simplicity with 308 transistor count and low power consumption of 1.10 mW.…”
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A Fault Tolerant Voter for Approximate Triple Modular Redundancy by Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee

“…With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.…”
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