SELF-OSCILLATING PARAMETRIC HUMIDITY SENSOR WITH FREQUENCY OUTPUT SIGNAL by Iaroslav Osadchuk, Alexander Osadchuk, Vladimir Osadchuk, Lyudmila Krylik

“… A self-oscillating parametric humidity sensor has been developed that implements the principle of "humidity-frequency" conversion into hybrid integrated circuit based on a microelectronic transistor structure with a negative differential resistance, in which the humidity-sensitive element is a resistor of the HR202 type. …”
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Switching circuit energy balance in iLabs on experimental lab server architecture by Li, Letitia Weixia

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Methods for compact modeling of process variations in silicon photonics devices by Martinez, Germain

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Investigation on Ultra-miniature and Ultra-low-power Non-invasive CMOS pH Sensor for Intracellular Monitoring by Zou, Xingyu

“…The intrinsic multilayer process and the dense transistor capacity of complementary metal oxide semiconductor (CMOS) technology has offered a great compact solution for miniaturized noninvasive pH sensors. …”
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Analog circuit optimization using evolutionary algorithms and convex optimization by Aggarwal, Varun

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Nanocrystalline Ge Flash Memories: Electrical Characterization and Trap Engineering by Kan, Eric Win Hong, Koh, B.H., Choi, Wee Kiong, Chim, Wai Kin, Antoniadis, Dimitri A., Fitzgerald, Eugene A.

“…In this work, a single transistor memory structure with threshold voltage shift, Vth, exceeding ~1.5 V corresponding to interface charge trapping in nc-Ge, operating at 0.96 MV/cm, is presented. …”
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Design of a continuous-time bandpass delta-sigma modulator by Yang, Xi, Ph. D. Massachusetts Institute of Technology

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Circuit analysis for camouflage netlists by Liu, YuCong

“…The most straight-forward algorithm (Brute-force) is not very effective for reverse engineering as the common IC chips that we use consist of billions of transistor in one package. Thus, the brute-force attack is too long, making the mentioned algorithm not economically viable for the malicious party. …”
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Design of a CMOS relaxation oscillator with reduced circuit sensitivity by Liao, Yizhuo

“…The oscillator includes a stable 2-Transistor based voltage reference without operational amplifier, a simple current reference employing the temperature-compensated composite resistor and the approximated Complementary-to-Absolute-Temperature (CTAT) delay based comparators compensate the approximated Proportional-to-Absolute-Temperature (PTAT) delay arising from the leakage currents in switches. …”
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Design of an ultra-low-voltage CMOS relaxation clock oscillator by Zhao, Bingbing

“…This dissertation presents the design of a 0.45 V fully-integrated relaxation oscillator using TSMC 40nm CMOS process technology. It comprises, a 2-Transistor (2-T) voltage reference, a current reference generator and a comparator in conjunction of the associated switched-capacitor network. …”
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Design of a digital PWM for digital class D amplifiers by Chue, Colin Jian Rong.

“…Additional delay elements and buffers were included as and where the source of problems occurred, and tuning the counter flip-flop transistor size was done to optimize the output response. …”
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Compact modeling of gate-all-around silicon nanowire MOSFETs by Lin Shihuan

“…An intrinsic long channel transistor drain current model is developed as the core model without charge-sheet approximation. …”
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Development of a low cost commercial switching mode power supply by Gopal Narayanamurthy.

“…In this switched-mode power supply switches a power transistor between saturation and cutoff with a variable duty cycle whose average is the desired output voltage. …”
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Vertical-SI-nanowire based nonvolatile flash memory for 3-D ultrahigh density application by Sun, Yuan

“…Among various cell structures, the Gate-All-Around (GAA) cylindrical nanowire (NW)- field effect transistor (FET) is being considered as one of the strong potential candidates to advance the NVM technology to the extreme miniaturization limits, due to the optimal electrostatic control which translates into nearly ideal subthreshold turn-on and a negligibly small short channel effect (SCE). …”
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Hardware development of 3 phase unity power factor ac -ac converter by Muhammad Fadzil Jamian.

“…The development of hardware will be the construction of the gate driver circuit for driving the Insulate Gate Bipolar Transistor modules. Recommendation by most manufacturers, the negative biasing needed in the voltage range of -15V to +15V to drive the IGBT module properly. …”
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HetNet enabled RF IC UWB-LNA design by Si Hao, Chow

“…The proposed design consists of a self-defined transistor core from the TSMC’s 40nm CMOS library, with the inclusion of a Resistor-Capacitor Drain-Gate feedback, coupled with Bridge-Shunt and Series Peaking techniques. …”
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Frequency compensation in an input folded cascode output buffered opamp by Phyo Wai Lin Kyaw@Lim Da Huang

“…In this project, the whole design consists of the wide swing constant transconductance biasing circuit to make sure every transistor is in their conducting region, a PMOS input folded cascode circuit as an OTA and a push-pull class AB output stage. …”
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Design and implementation of voltage regulator for a power supply by Chua, Meng Lim

“…Linear regulators being researched and implemented are series voltage regulator, shunt voltage regulator, transistor shunt voltage regulator, fixed regulator and variable regulator. …”
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Memristor switching model for digital and analog circuits / Siti Musliha Ajmal Mokhtar by Ajmal Mokhtar, Siti Musliha

“…Scaling of complementary-metal-oxide-semiconductor (CMOS) transistor for higher performance device is nearly reaching its limit due to technology limitation issues. …”
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SVX4: A new deep-submicron readout IC for the Tevatron collider at fermilab by Krieger, B, Alfonsi, S, Bacchetta, N, Christofek, S, Garcia-Sciveres, M, Haber, C, Hanagaki, K, Hoff, J, Johnson, M, von der Lippe, H, Lujan, P, Mandelli, E, Meng, G, Nomerotski, A, Pellet, D, Rapidis, P, Utes, M, Walder, J, Weber, M, Wester, W, Wilkes, T, Yarema, R, Yao, W, Zimmerman, T

“…Whereas SVX3D was fabricated in a 0.8-mum radiation-hard process, SVX4 was fabricated in a standard 0.25-mum mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the CERN RD49 collaboration. …”