Showing 121 - 140 results of 882 for search '(((((farr OR farm) OR ((fabry OR harry) OR (barry OR carry))) OR full) OR far) OR air) 40', query time: 0.21s Refine Results
  1. 121

    Ultra-low power CMOS circuit for IoT by Lau, Fong Hou

    Published 2019
    “…Furthermore, the few proposed full adder topologies will go through simulations under the 40nm Cadence Virtuoso software based on nominal voltage supply of 1V to be scaled down to 0.45V or as low as possible till the output signal gets degraded. …”
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    Final Year Project (FYP)
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    High speed low power CMOS data compressor design and analysis by Radhakrishnan, Sathiya Priyanka

    Published 2019
    “…In this dissertation, different topologies of same one bit full adder performance is analysed in terms of total power consumption which includes static and dynamic power consumption, total delay which is the average of rise time and fall time delay and power delay product in the supply voltage range of 900mV to 1.1V and frequency range of 250 MHz to 1 GHz, as the specified standard operating voltage by TSMC for 40 nm node technology is 1.1 V. …”
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    Thesis
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