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The relationship between the moderate–heavy boundary and critical speed in running
Published 2024“…While estimates of the heavy- and severe-intensity boundary, that is, the critical speed (CS), can be derived from habitual training, determining the moderate–heavy boundary or first threshold (T1) requires testing, which can be costly and time-consuming. …”
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Article -
82
The impact of programme management on the speed of AI development in semiconductor industries
Published 2024Subjects:Thesis -
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Speeding up convolutional neural networks with low rank expansions
Published 2014Internet publication -
84
Load‑bearing behaviors of sandwich plates with non‑uniformly distributed grid cores : Static compression and bending
Published 2023“…Under bending loading, most NUGPs experience local failure at the loading head, while the specific category surpassing GPs undergoes shear buckling in longer grid walls. (3) Deformation modes of the core layer, mechanical analysis, thin plate buckling theory, and equivalent bending stiffness calculations elucidate the load-bearing mechanisms of NUGPs. These findings enhance topology optimization research for sandwich plates, provide guidance for grid wall arrangements under different loading conditions, and offer insights for designing lightweight sandwich structures.…”
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Article -
85
Speeding up deep neural network training with decoupled and analytic learning
Published 2021“…The BP requires a sequential passing of activations and gradients, which has been recognized as lockings (i.e., the forward, backward, and update lockings). …”
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Thesis-Doctor of Philosophy -
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High-speed cruise missiles in Asia : evolution or revolution in fire power?
Published 2014“…Recent reports indeicated that China has successfully tested a hypersonic system - a potential precursor for a high-speed cruise missile. What is the role of high-speed cruise missiles in providing firepower for land-attack missions?…”
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Commentary -
91
Pipelined adder graph optimization for high speed multiple constant multiplication
Published 2013“…This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. …”
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Conference Paper -
92
Higher-order sliding mode observer for speed and position estimation in PMSM
Published 2014“…This paper presents a speed and position estimation method for the permanent magnet synchronous motor (PMSM) based on higher-order sliding mode (HOSM) observer. …”
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Journal Article -
93
Design of high speed advanced encryption standard (AES) encryption circuit
Published 2022“…The proposed optimized high-speed 128-bit AES encryption circuit has a throughput about 5 times higher than the standard design.…”
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Thesis-Master by Coursework -
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Traffic speed characteristics around road humps in Nanyang Technological University
Published 2009Get full text
Final Year Project (FYP) -
95
Speeding up secure web transactions using elliptic curve cryptography
Published 2010Get full text
Final Year Project (FYP) -
96
Pre-planned recovery schemes with delay consideration for high speed networks
Published 2008Get full text
Thesis -
97
Actively mode-locked fiber lasers for high speed telecommunication systems
Published 2010Get full text
Thesis -
98
Investigation into the effect of process parameter on properties of AM parts - scan speed
Published 2016“…An experiment was conducted to investigate the influence of the laser scan speed on the mechanical properties of the printed parts.…”
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Final Year Project (FYP) -
99
High speed low power CMOS data compressor design and analysis
Published 2019“…This dissertation aims in studying and analysing of lower power high-speed CMOS circuit for which full adder of different topologies are constructed to finally cascade it to form 4:2 and 8:2 CMOS data compressor. …”
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Thesis -
100
An enhanced low-power high-speed adder for error-tolerant application
Published 2010“…It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test—Error- Tolerance (ET), we managed to develop a novel Error-Tolerant Adder which we named the Type II (ETAII). …”
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Conference Paper