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  1. 101

    A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT by Hu, Yusong, Jong, Ching Chuen

    Published 2013
    “…The synthesis results in 90 nm CMOS process show that the proposed architecture achieves a better area-delay product by 60% and higher throughput by 97% when compared to the best existing design for the CDF (Cohen-Daubechies-Favreau) 9/7 2-D DWT.…”
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    Journal Article
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