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    High speed low power CMOS data compressor design and analysis by Radhakrishnan, Sathiya Priyanka

    Published 2019
    “…In this dissertation, different topologies of same one bit full adder performance is analysed in terms of total power consumption which includes static and dynamic power consumption, total delay which is the average of rise time and fall time delay and power delay product in the supply voltage range of 900mV to 1.1V and frequency range of 250 MHz to 1 GHz, as the specified standard operating voltage by TSMC for 40 nm node technology is 1.1 V. …”
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    Thesis
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