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    Ultra-low power CMOS circuit for IoT by Lau, Fong Hou

    Published 2019
    “…Furthermore, the few proposed full adder topologies will go through simulations under the 40nm Cadence Virtuoso software based on nominal voltage supply of 1V to be scaled down to 0.45V or as low as possible till the output signal gets degraded. …”
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    Final Year Project (FYP)
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    Diagrammatic Representation and Inference : 12th International Conference, Diagrams 2021, Virtual, September 28-30, 2021, Proceedings / by Diagrams (Conference) (12th : 2021 : Online) 643173, Basu, Amrita, 1953-, editor 643175, Stapleton, Gem, editor 643176, Linker, Sven, editor 643177, Legg, Catherine, editor 643178, Manalo, Emmanuel, editor 643179, Viana, Petrucio, editor 643180

    Published [202
    “…This book constitutes the refereed proceedings of the 12th International Conference on the Theory and Application of Diagrams, Diagrams 2021, held virtually in September 2021. The 16 full papers and 25 short papers presented together with 16 posters were carefully reviewed and selected from 94 submissions. …”
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