Showing 21 - 40 results of 555 for search '((farr OR (fair OR (fail OR (fall OR full)))) OR far) 40', query time: 0.16s Refine Results
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    Design of ultra low power 1-bit full adder cell for logic devices by Kumar, Abhishek

    Published 2019
    “…This in turn lead to development of an application which proved useful in substantial power consumption reduction in 1-bit Full Adder cell.…”
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    Thesis
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    Solid-State P NMR, Far-IR, and Structural Studies on Two-Coordinate (Tris(2,4,6-trimethoxyphenyl)phosphine)copper(I) Chloride and Bromide by Bowmaker, Graham A., Cotton, John D., Healy, Peter C., Kildea, John D.

    Published 1989
    “…The spectrum for each complex shows an asymmetric quartet centered at -65 ppm with highly asymmetric line spacings of 1.40, 2.21, and 2.50 kHz and 1.48, 2.17, and 2.43 kHz, respectively. …”
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    High speed low power CMOS data compressor design and analysis by Radhakrishnan, Sathiya Priyanka

    Published 2019
    “…In this dissertation, different topologies of same one bit full adder performance is analysed in terms of total power consumption which includes static and dynamic power consumption, total delay which is the average of rise time and fall time delay and power delay product in the supply voltage range of 900mV to 1.1V and frequency range of 250 MHz to 1 GHz, as the specified standard operating voltage by TSMC for 40 nm node technology is 1.1 V. …”
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    Thesis
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