Representation theoretic interpretation and interpolation properties of inhomogeneous spin q-Whittaker polynomials by Korotkikh, Sergei

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Performant almost-latch-free data structures using epoch protection in more depth by Li, Tianyu, Chandramouli, Badrish, Madden, Samuel

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Microlensing of Strongly Lensed Quasars by Vernardos, G., Sluse, D., Pooley, D., Schmidt, R. W., Millon, M., Weisenbach, L., Motta, V., Anguita, T., Saha, P., O’Dowd, M., Peel, A., Schechter, P. L.

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Constrained neuro fuzzy inference methodology for explainable personalised modelling with applications on gene expression data by Singh, Balkaran, Doborjeh, Maryam, Doborjeh, Zohreh, Budhraja, Sugam, Tan, Samuel, Sumich, Alexander, Goh, Wilson, Lee, Jimmy, Lai, Edmund, Kasabov, Nikola

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A Direct Optimization Algorithm for Input-Constrained MPC by Wu, Liang, Braatz, Richard D

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Depth-optimized quantum circuits for ASCON: AEAD and HASH † by Oh, Yujin, Jang, Kyungbae, Baksi, Anubhab, Seo, Hwajeong

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Randomness and early termination: what makes a game exciting? by Guo, G, Howison, S, Possamai, D, Reisinger, C

Amplifying signals in the tumor microenvironment for drug development and diagnostics by Martin Alonso, Maria Carmen

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Ultra-low power CMOS circuit for IoT by Lau, Fong Hou

“…Furthermore, the few proposed full adder topologies will go through simulations under the 40nm Cadence Virtuoso software based on nominal voltage supply of 1V to be scaled down to 0.45V or as low as possible till the output signal gets degraded. …”
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Stochastic Dynamics on Integrable Lattice Models by Nicoletti, Matthew S.

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Convexity of Solvability Set of Power Distribution Networks by Dymarsky, Anatoly, Turitsyn, Konstantin

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Petz recovery from subsystems in conformal field theory by Vardhan, Shreya, Wei, Annie Y., Zou, Yijian

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High speed low power CMOS data compressor design and analysis by Radhakrishnan, Sathiya Priyanka

“…In this dissertation, different topologies of same one bit full adder performance is analysed in terms of total power consumption which includes static and dynamic power consumption, total delay which is the average of rise time and fall time delay and power delay product in the supply voltage range of 900mV to 1.1V and frequency range of 250 MHz to 1 GHz, as the specified standard operating voltage by TSMC for 40 nm node technology is 1.1 V. …”
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High-performance partially aligned semiconductive single-walled carbon nanotube transistors achieved with a parallel technique by Wang, Yilei, Pillai, Suresh Kumar Raman, Chan-Park, Mary B.

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Human comfort in indoor environment : a review on assessment criteria, data collection and data analysis methods by Song, Ying, Mao, Fubing, Liu, Qing

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An ultrastable lithium metal anode enabled by designed metal fluoride spansules by Yuan, Huadong, Nai, Jianwei, Tian, He, Ju, Zhijin, Zhang, Wenkui, Liu, Yujing, Tao, Xinyong, Lou, David Xiong Wen

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Android mobile-platform-based image reconstruction for photoacoustic tomography by Hui, Xie, Rajendran, Praveenbalaji, Muhamad Ar Iskandar Zulkifli, Ling, Tong, Pramanik, Manojit

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Designing initiatives for vulnerable families : from theory to design in Sydney, Australia by Eastwood, John Graeme, De Souza, Denise E., Shaw, Miranda, Garg, Pankaj, Woolfenden, Susan, Tyler, Ingrid, Kemp, Lynn A.

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Overseas investment : the Singapore experience in China, India and Vietnam. by Chow, Serene Wai Lyn., Lum, Weng Jing., Phua, Marianne Hui Chen.

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Novel frequency selective structures based on a two-dimensional periodic array of vertical microstrip lines by Amir Khurrum Rashid

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