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    Speed, power and area optimized monotonic asynchronous array multipliers by Balasubramanian, Padmanabhan, Mastorakis, Nikos E.

    Published 2024
    “…The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. …”
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    Journal Article
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    Design of phase locked loop with PVT tolerance by Chong, Kok Foong

    Published 2012
    “…The frequency variation with respect to the same control voltage is reduced to ±3.9% across all the PVT variation from -40°C to 125°C. VCO dummies are normally added to the VCO in order to provide a uniform loading for each VCO delay stage. …”
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    Thesis
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    Diagrammatic Representation and Inference : 12th International Conference, Diagrams 2021, Virtual, September 28-30, 2021, Proceedings / by Diagrams (Conference) (12th : 2021 : Online) 643173, Basu, Amrita, 1953-, editor 643175, Stapleton, Gem, editor 643176, Linker, Sven, editor 643177, Legg, Catherine, editor 643178, Manalo, Emmanuel, editor 643179, Viana, Petrucio, editor 643180

    Published [202
    “…This book constitutes the refereed proceedings of the 12th International Conference on the Theory and Application of Diagrams, Diagrams 2021, held virtually in September 2021. The 16 full papers and 25 short papers presented together with 16 posters were carefully reviewed and selected from 94 submissions. …”
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