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    High speed low power CMOS data compressor design and analysis by Radhakrishnan, Sathiya Priyanka

    Published 2019
    “…These schematic simulations are done in Cadence Virtuoso software with TSMC 40nm technology library and the results are studied and concluded saying transmission gate, dynamic logic and 10T XOR gates show better results among all in which transmission gate logic showed good performance results used to construct 4:2 and 8:2 CMOS data compressor.…”
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    Thesis
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