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    A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI by Ji, Yuxin, Zhang, Yuhang, Chen, Changyan, Zhao, Jian, Rokhani, Fakhrul Zaman, Ismail, Yehea, Li, Yongfu

    Published 2024
    “…This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. …”
    Article
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