Fast timing analysis of clock networks considering environmental uncertainty by Wang, Hai, Yu, Hao, Tan, Sheldon X. D.

“…This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verification of clock-skew by an incremental-SVD-based compact modeling assisted with adaptive sampling. …”
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Low power CMOS multiplier IC design by Zhang, Wanqing

“…The design of low-power multipliers will be carried out through two ways: improving the structure of the multiplier and the clock cycle. …”
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Piezoelectric energy harvesting for low power electronic devices by Lim, Wilson Benedict Ye Xiang.

“…This FYP is dealing with piezoelectric energy generation which can be used for powering low energy devices such as remote controllers, clocks, mp3 etc. …”
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Low-power flip-flop circuits for high-performance systems by Tang, Pey Chyi.

“…The design of a flip-flop with low power consumption and high speed had become a major concern as there is a continuous increase of clock frequency, chip density and pipeline stages. …”
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Data-driven dynamic logic for low power adders and multipliers by Mahendiran Navasakthi

“…For high speed operation, clocks are mandatory in digital circuits. In case of dynamic logic, the presence of clock, increases the speed but causes higher power dissipation. …”
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Real time power system simulation using Opal-RT by Shi, Donghan

“…The power system model consists of generators, power distribution lines, transformers, power electronics converters and loads on both AC and DC buses. …”
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16-bit low-power CMOS multiplier IC design by Zhang, Jingyao

“…In summary, the improved adder design and the carry save adder array contributed to the lower power consumption and the shorter delay of the multiplier, and the sequential Wallace tree multiplier further improves the power efficiency by eliminating unnecessary switching activities, and it introduced a flexible control over the balance of power and performance through the adjustment of clock speed.…”
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Speed, power and area optimized monotonic asynchronous array multipliers by Balasubramanian, Padmanabhan, Mastorakis, Nikos E.

“…Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). …”
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Low power digital CMOS design based on adiabatic switching principles by Wang, Wen Yuan.

“…Adiabatic or energy recovery circuit design is a relatively new method to implement adiabatic switching concepts to achieve low power dissipation in integrated circuits. It accomplishes this goal by using an alternating voltage source to charge and discharge logic state-holding capacitances through small voltage drops. …”
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Low-power reference circuit design for integrated DC-DC converters by Tham, Yong Hao

“…The process sensitivity, (𝜎/𝜇) is expected to be lower than the Monte Carlo simulation results of 5.02% in post-fabrication measurements with the advantage of precisely fabricated capacitor and an accurate clock reference. …”
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ASIC implementation of a high speed and low power scalar product computation unit by Low, Jeremy Yung Shern.

“…The synthesized design has latency of two clock cycles with minimum clock period of 5.25ns and thus total delay of 10.5ns. …”
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Optimizing Android smartphone’s user experience and power efficiency through governor and scheduler customization by Koh, Nicholas Ming Xuan

“…This concept enables processes to boost the CPU clock speeds, in turn possibly getting optimal user experience. …”
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Design of a supply- and temperature-invariant capacitive sensor interface for low power applications by Arup Kocheethra George

“…Several existing high-resolution and low-power capacitive sensing systems require assisting circuit blocks such as clock sources, decimation filters and supply regulation/temperature compensation circuits for their operation. …”
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A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring by Liu, Xin, Zhou, Jun, Yang, Yongkui, Wang, Bo, Lan, Jingjing, Wang, Chao, Luo, Jianwen, Goh, Wang Ling, Kim, Tony Tae-Hyoung, Je, Minkyu

“…An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. …”
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Design of test setup for asynchronous digital signal processor by Chua, Qijing.

“…Asynchronous systems do not have a global clock, thus eliminating the problems of clock distribution, clock skew and reducing power dissipation. …”
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FPGA-based multi-rate system design : Avalon Interface vs.Globally Asynchronous Locally Synchronous approach by Zou, You.

“…On the other hand, the potential for GALS (pausible clock) approach in power consumption reduction should also be paid special attention to. …”
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Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control by Chua, Dillon Yu Ze

“…It is also less likely to accumulate jitter from power-supply and substrate noise. The quality of clock pulses is measured by frequency, phase, duty-cycle, jitter, and clock skew in general.…”
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Synthesis and testing of asynchronous circuits - micropipeline by Khaing, Kathy.

“…Since asynchronous circuits having no globally distributed clock, there are no problems about the clock skew occurring in synchronous systems. …”
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8 bit asynchronous SAR ADC by Mahesha, Ballaki Aditya

“…This ADC is engineered to resolve signals up to 100 MHz and can perform conversions at a clock speed of 200 MHz. The ADC is optimized for low power consumption, operating within a power supply range of 1.8 to 1.5V, and features a reference voltage set at 1V. …”
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Design of phase locked loop with PVT tolerance by Chong, Kok Foong

“…The compensation circuitry is of small area and does not consume significant extra power. To verify the proposed compensation techniques in VCO design, a fully-integrated PLL clock generator has been designed for 1GHz~3GHz general purpose clock generation using IBM’s 0.13µm CMOS 8RF process. …”
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