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    FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs

    FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs by Grabinski, Wladek, Scholz, Rene, Verley, Jason, Keiter, Eric R., Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal Singh, Torri, Guilherme B., Tomaszewski, Daniel, Bucher, Matthias, Sallese, Jean-Michel, Muller, Markus, Kuthe, Pascal, Krattenmacher, Mario

    Published 2024
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    Conference or Workshop Item

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