VHDL design of a floating-point arithmetic unit for implementation in an FPGA-based system /

VHDL design of a floating-point arithmetic unit for implementation in an FPGA-based system /

Project Paper (Bachelor of Electrical Engineering (Electronics)) - Universiti Teknologi Malaysia, 2003

Bibliographic Details
Main Author: 431865 Ian Kree Ensalie @ Mambak
Format:
Language:eng
Published: Skudai : Universiti Teknologi Malaysia, 2003
Subjects:
Floating-point arithmetic
VHDL (Computer hardware description language)

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