Verification by error modeling : using testing techniques in hardware verification /

Verification by error modeling : using testing techniques in hardware verification /

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Detalhes bibliográficos
Principais autores: 461327 Radecka, Katarzyna, Zilic, Zeljko
Formato:
Idioma:eng
Publicado em: Dordrecht : Kluwer Academic Pubs., 2003
Assuntos:
Integrated circuits
Error analysis (Mathematics)

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