Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing [electronic resource] /
Thesis (Sarjana Kejuruteraan (Elektrik)) - Universiti Teknologi Malaysia, 2007
| Main Author: | |
|---|---|
| Format: | |
| Language: | eng |
| Published: |
Skudai : Universiti Teknologi Malaysia,
2007
|
| Subjects: |