Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) /
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005
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| Format: | |
| Language: | eng |
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Skudai : Universiti Teknologi Malaysia,
2005
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| _version_ | 1826363134250582016 |
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| author | 226132 Chrishanton Vethanayagam |
| author_facet | 226132 Chrishanton Vethanayagam |
| author_sort | 226132 Chrishanton Vethanayagam |
| collection | OCEAN |
| description | Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005 |
| first_indexed | 2024-03-04T14:30:14Z |
| format | |
| id | KOHA-OAI-TEST:40632 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-04T14:30:14Z |
| publishDate | 2005 |
| publisher | Skudai : Universiti Teknologi Malaysia, |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:406322020-12-19T16:57:34ZDesign & implementation (VLSI) of an all digital phase locked loop (ADPLL) / 226132 Chrishanton Vethanayagam Skudai : Universiti Teknologi Malaysia,2005engProject Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 200516FEELECTLIntegrated circuitsPhase-locked loops |
| spellingShingle | Integrated circuits Phase-locked loops 226132 Chrishanton Vethanayagam Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) / |
| title | Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) / |
| title_full | Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) / |
| title_fullStr | Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) / |
| title_full_unstemmed | Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) / |
| title_short | Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) / |
| title_sort | design implementation vlsi of an all digital phase locked loop adpll |
| topic | Integrated circuits Phase-locked loops |
| work_keys_str_mv | AT 226132chrishantonvethanayagam designimplementationvlsiofanalldigitalphaselockedloopadpll |