Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) /

Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) /

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005

Bibliographic Details
Main Author:	226132 Chrishanton Vethanayagam
Format:
Language:	eng
Published:	Skudai : Universiti Teknologi Malaysia, 2005
Subjects:	Integrated circuits Phase-locked loops

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