Digital System Design With SystemVerilog /

To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL) and todays most powerful, useful HDL is SystemVerilog, now an IEEE standard.Digital System Design with SystemVerilogis the first comprehensive introduction to both S...

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Bibliographic Details
Main Author: Zwolinski, Mark, author 327189
Format:
Language:eng
Published: Upper Saddle River, NJ : Addison-Wesley, 2010
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Summary:To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL) and todays most powerful, useful HDL is SystemVerilog, now an IEEE standard.Digital System Design with SystemVerilogis the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it. Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org.