Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) /
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2016
| Main Authors: | , , |
|---|---|
| Format: | |
| Language: | eng |
| Published: |
2016
|
| Subjects: |