Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) /
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2016
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| Language: | eng |
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2016
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| _version_ | 1826464104407105536 |
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| author | Tim, Wei Lun, 1992-, author Norlina Paraman, supervisor Fakulti Kejuruteraan Elektrik |
| author_facet | Tim, Wei Lun, 1992-, author Norlina Paraman, supervisor Fakulti Kejuruteraan Elektrik |
| author_sort | Tim, Wei Lun, 1992-, author |
| collection | OCEAN |
| description | Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2016 |
| first_indexed | 2024-03-05T15:14:54Z |
| format | |
| id | KOHA-OAI-TEST:534631 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-05T15:14:54Z |
| publishDate | 2016 |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:5346312020-12-19T17:20:09ZDesign for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / Tim, Wei Lun, 1992-, author Norlina Paraman, supervisor Fakulti Kejuruteraan Elektrik 2016engProject Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2016Includes bibliographical referencesFEELECTLCombinational circuits |
| spellingShingle | Combinational circuits Tim, Wei Lun, 1992-, author Norlina Paraman, supervisor Fakulti Kejuruteraan Elektrik Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / |
| title | Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / |
| title_full | Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / |
| title_fullStr | Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / |
| title_full_unstemmed | Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / |
| title_short | Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR) / |
| title_sort | design for testability dft method at register transfer level design for greatest common divisor gcd and finite impulse response fir |
| topic | Combinational circuits |
| work_keys_str_mv | AT timweilun1992author designfortestabilitydftmethodatregistertransferleveldesignforgreatestcommondivisorgcdandfiniteimpulseresponsefir AT norlinaparamansupervisor designfortestabilitydftmethodatregistertransferleveldesignforgreatestcommondivisorgcdandfiniteimpulseresponsefir AT fakultikejuruteraanelektrik designfortestabilitydftmethodatregistertransferleveldesignforgreatestcommondivisorgcdandfiniteimpulseresponsefir |