Verilog design of A 256-BIT AES crypto processor core /
Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Universiti Teknologi Malaysia, 2007
Main Author: | |
---|---|
Format: | |
Language: | eng |
Published: |
Skudai : Universiti Teknologi Malaysia,
2007
|
Subjects: | |
Online Access: | http://www.psz.utm.my/sla/billing/login.asp?mid=50965 |