A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (Vdd) optimization...
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| Format: | Article |
| Language: | English English |
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American Scientific Publishers
2017
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| Online Access: | http://umpir.ump.edu.my/id/eprint/15045/1/16JNN-12608.pdf http://umpir.ump.edu.my/id/eprint/15045/7/ftech-yasir-2017.pdf |