Optimization of n-MOS 6T nanowire SRAM bit cell based on nanowires ratio of SiNWTs
In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possi...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Sumy State University
2020
|
| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/30511/1/Optimization%20of%20n-MOS%206T%20nanowire%20SRAM%20bit%20cell.pdf |