A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling ti...

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Bibliographic Details
Main Authors: Hyein Kang, Sewon Lee, Minjae Lee
Format: Article
Language:English
Published: MDPI AG 2023-04-01
Series:Electronics
Subjects:
asynchronous
SAR ADC
delay circuit
tapered
DAC settling
Online Access:https://www.mdpi.com/2079-9292/12/8/1863

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https://www.mdpi.com/2079-9292/12/8/1863

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