A 0.0012 mm<sup>2</sup> 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

A 0.0012 mm<sup>2</sup> 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

This paper presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. By utilizing the output of the dynamic amplifier (DA) to generate an asynchronous clock, the reset time for the...

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Bibliographic Details
Main Authors: Eun-Ji An, Dong-Ryeol Oh
Format: Article
Language:English
Published: MDPI AG 2022-05-01
Series:Electronics
Subjects:
asynchronous clock
loop-unrolled SAR
dynamic amplifier
calibration free
inverter-inserted comparator
split latch
Online Access:https://www.mdpi.com/2079-9292/11/11/1707

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https://www.mdpi.com/2079-9292/11/11/1707

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