Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only c...

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Bibliographic Details
Main Authors: Xiang Wang, Zongmin Zhao, Dongdong Xu, Zhun Zhang, Qiang Hao, Mengchen Liu, Yu Si
Format: Article
Language:English
Published: MDPI AG 2020-07-01
Series:Electronics
Subjects:
embedded processor
program execution security
integrity check
fault recovery
checkpoint backup
checkpoint rolling back
Online Access:https://www.mdpi.com/2079-9292/9/7/1165

Internet

https://www.mdpi.com/2079-9292/9/7/1165

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