A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be r...

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Bibliographic Details
Main Authors: Poki Chen, Joshua Adiel Wijaya, Seiji Kajihara, Trio Adiono, Hsiang-Yu Chen, Ruei-Ting Wang, Yousuke Miyake
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Field programmable gate array (FPGA)
merged TDL
phase selection
phase sorting
phase wrapping
time-to-digital converter
Online Access:https://ieeexplore.ieee.org/document/9967976/

Internet

https://ieeexplore.ieee.org/document/9967976/

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