Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors
Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, es...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-03-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/23/6/3212 |
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| author | Hanshui Fan Xuan Tian Huiting Peng Yinfeng Shen Liang Li Ming Li Liming Gao |
| author_facet | Hanshui Fan Xuan Tian Huiting Peng Yinfeng Shen Liang Li Ming Li Liming Gao |
| author_sort | Hanshui Fan |
| collection | DOAJ |
| description | Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>V</mi><mrow><mi>b</mi><mi>l</mi></mrow></msub></mrow></semantics></math></inline-formula>) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>V</mi><mrow><mi>b</mi><mi>l</mi></mrow></msub></mrow></semantics></math></inline-formula> countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>V</mi><mrow><mi>b</mi><mi>l</mi></mrow></msub></mrow></semantics></math></inline-formula> scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability. |
| first_indexed | 2024-03-11T05:54:56Z |
| format | Article |
| id | doaj.art-0481d6cca32d451f822793397f9fe891 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-11T05:54:56Z |
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| spelling | doaj.art-0481d6cca32d451f822793397f9fe8912023-11-17T13:47:30ZengMDPI AGSensors1424-82202023-03-01236321210.3390/s23063212Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based SensorsHanshui Fan0Xuan Tian1Huiting Peng2Yinfeng Shen3Liang Li4Ming Li5Liming Gao6Institute of Microelectronic Material & Technology, School of Material Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, ChinaSanDisk Information Technology Co., Ltd., Shanghai 200241, ChinaInstitute of Microelectronic Material & Technology, School of Material Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, ChinaInstitute of Microelectronic Material & Technology, School of Material Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, ChinaSanDisk Information Technology Co., Ltd., Shanghai 200241, ChinaInstitute of Microelectronic Material & Technology, School of Material Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, ChinaInstitute of Microelectronic Material & Technology, School of Material Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, ChinaThree-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>V</mi><mrow><mi>b</mi><mi>l</mi></mrow></msub></mrow></semantics></math></inline-formula>) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>V</mi><mrow><mi>b</mi><mi>l</mi></mrow></msub></mrow></semantics></math></inline-formula> countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>V</mi><mrow><mi>b</mi><mi>l</mi></mrow></msub></mrow></semantics></math></inline-formula> scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability.https://www.mdpi.com/1424-8220/23/6/32123D NAND flash memorybitline voltagechannel potentialDIBL effectdevice modelMONOS |
| spellingShingle | Hanshui Fan Xuan Tian Huiting Peng Yinfeng Shen Liang Li Ming Li Liming Gao Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors Sensors 3D NAND flash memory bitline voltage channel potential DIBL effect device model MONOS |
| title | Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors |
| title_full | Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors |
| title_fullStr | Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors |
| title_full_unstemmed | Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors |
| title_short | Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors |
| title_sort | adaptive bitline voltage countermeasure for neighbor wordline interference in 3d nand flash memory based sensors |
| topic | 3D NAND flash memory bitline voltage channel potential DIBL effect device model MONOS |
| url | https://www.mdpi.com/1424-8220/23/6/3212 |
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