Practical System-on-Chip Repeater Design With Hybrid Meta-Heuristic Techniques

Practical System-on-Chip Repeater Design With Hybrid Meta-Heuristic Techniques

This paper recommends a practical way to insert buffer and flop repeaters onto global signals of a complex system-on-chip (SoC). With the advent of deep sub-micrometer technology and new business environment, the market prefers a highly integrated SoC with fast design productivity and low developmen...

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Bibliographic Details
Main Authors: Eng Keong Teh, Mohamad Adzhar Md Zawawi, Mohamed Fauzi Packeer Mohamed, Nor Ashidi Mat Isa
Format: Article
Language:English
Published: IEEE 2018-01-01
Series:IEEE Access
Subjects:
Artificial intelligent
buffer repeater
deep sub-micrometer
flop repeater
hybrid meta-heuristic
system-on-a-chip (SoC)
Online Access:https://ieeexplore.ieee.org/document/8444367/

Internet

https://ieeexplore.ieee.org/document/8444367/

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