FPGA-based ML adaptive accelerator: A partial reconfiguration approach for optimized ML accelerator utilization

FPGA-based ML adaptive accelerator: A partial reconfiguration approach for optimized ML accelerator utilization

The relentless increase in data volume and complexity necessitates advancements in machine learning methodologies that are more adaptable. In response to this challenge, we present a novel architecture enabling dynamic classifier selection on FPGA platforms. This unique architecture combines hardwar...

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Bibliographic Details
Main Authors: Achraf El Bouazzaoui, Abdelkader Hadjoudja, Omar Mouhib, Nazha Cherkaoui
Format: Article
Language:English
Published: Elsevier 2024-03-01
Series:Array
Subjects:
Field programmable gate array
Partial reconfiguration
Reconfigurable hardware
Machine learning
Dynamic classifier selection
Online Access:http://www.sciencedirect.com/science/article/pii/S2590005624000031

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http://www.sciencedirect.com/science/article/pii/S2590005624000031

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