Tri-gate junctionless transistors with electrostatically highly doped channel
Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically hi...
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| Format: | Article |
| Language: | English |
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AIP Publishing LLC
2023-11-01
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| Series: | AIP Advances |
| Online Access: | http://dx.doi.org/10.1063/5.0174553 |
| _version_ | 1797404750971404288 |
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| author | Dae-Young Jeon |
| author_facet | Dae-Young Jeon |
| author_sort | Dae-Young Jeon |
| collection | DOAJ |
| description | Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (Vgb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes. |
| first_indexed | 2024-03-09T02:59:36Z |
| format | Article |
| id | doaj.art-065bf89a3b50436796cbbd985eaca07d |
| institution | Directory Open Access Journal |
| issn | 2158-3226 |
| language | English |
| last_indexed | 2024-03-09T02:59:36Z |
| publishDate | 2023-11-01 |
| publisher | AIP Publishing LLC |
| record_format | Article |
| series | AIP Advances |
| spelling | doaj.art-065bf89a3b50436796cbbd985eaca07d2023-12-04T17:18:28ZengAIP Publishing LLCAIP Advances2158-32262023-11-011311115010115010-410.1063/5.0174553Tri-gate junctionless transistors with electrostatically highly doped channelDae-Young Jeon0Department of Electrical Engineering, Gyeongsang National University, Jinju 52828, Gyeongnam, Republic of KoreaMultiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (Vgb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes.http://dx.doi.org/10.1063/5.0174553 |
| spellingShingle | Dae-Young Jeon Tri-gate junctionless transistors with electrostatically highly doped channel AIP Advances |
| title | Tri-gate junctionless transistors with electrostatically highly doped channel |
| title_full | Tri-gate junctionless transistors with electrostatically highly doped channel |
| title_fullStr | Tri-gate junctionless transistors with electrostatically highly doped channel |
| title_full_unstemmed | Tri-gate junctionless transistors with electrostatically highly doped channel |
| title_short | Tri-gate junctionless transistors with electrostatically highly doped channel |
| title_sort | tri gate junctionless transistors with electrostatically highly doped channel |
| url | http://dx.doi.org/10.1063/5.0174553 |
| work_keys_str_mv | AT daeyoungjeon trigatejunctionlesstransistorswithelectrostaticallyhighlydopedchannel |