Computational Failure Analysis of In-Memory RRAM Architecture for Pattern Classification CNN Circuits

Computational Failure Analysis of In-Memory RRAM Architecture for Pattern Classification CNN Circuits

Power-efficient data processing subsystems performing millions of complex concurrent arithmetic operations per second form part of today’s essential solution required to meet the growing demand of edge computing applications, given the volume of data collected by real-time Internet-Of-Thi...

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Bibliographic Details
Main Authors: Nagaraj Lakshmana Prabhu, Nagarajan Raghavan
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Resistive RAM
convolution neural network
look-up-table
in-memory computation
image classification
Internet of Things
Online Access:https://ieeexplore.ieee.org/document/9654206/

Internet

https://ieeexplore.ieee.org/document/9654206/

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