Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design
This study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-cha...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2024-03-01
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| Series: | Alexandria Engineering Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S1110016824001169 |
| _version_ | 1797320939082350592 |
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| author | Abdelrahman Elshamy Ahmed Shaker Yasmine Elogail Marwa S. Salem Mona El Sabbagh |
| author_facet | Abdelrahman Elshamy Ahmed Shaker Yasmine Elogail Marwa S. Salem Mona El Sabbagh |
| author_sort | Abdelrahman Elshamy |
| collection | DOAJ |
| description | This study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-channel interface. This technique leads to improved tunneling rates and increased current handling capability. The simulation analysis focuses on optimizing the position and dimension of the high-k dielectric pocket to enhance key device characterization metrics such as ON-state current (ION), ON-to-OFF-state current ratio (ION/IOFF), subthreshold swing (SS), and cutoff frequency (fT). The resulting optimized design for a 30 nm-channel length involves a pocket shift of 1 nm and a pocket length of 12 nm. This configuration achieves a remarkable ON current of 55 µA/µm, which is 30 times higher than that of a conventional TFET. Importantly, other analog performance parameters remain unaffected, with fT surpassing 175 GHz for the 30 nm-channel. Additionally, transient analysis is conducted by applying a resistive load inverter circuit to a pulse input. The fall propagation delay (tphl) exhibits a greater than two orders of magnitude enhancement, along with improved overshoot voltage (VP) compared to a TFET without a pocket. The study further explores the impact of supply scaling on transient parameters. Optimal pocket scalability concerning channel length is found to be 40% for pocket length and approximately 2.5% for pocket shift relative to the source-channel interface. The proposed design significantly enhances DC and analog as well as circuit-level metrics compared to the traditional uniform gate oxide TFET. |
| first_indexed | 2024-03-08T04:51:15Z |
| format | Article |
| id | doaj.art-08be48c7dd4d499e9bd259eca106a766 |
| institution | Directory Open Access Journal |
| issn | 1110-0168 |
| language | English |
| last_indexed | 2024-03-08T04:51:15Z |
| publishDate | 2024-03-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Alexandria Engineering Journal |
| spelling | doaj.art-08be48c7dd4d499e9bd259eca106a7662024-02-08T05:04:51ZengElsevierAlexandria Engineering Journal1110-01682024-03-01913038Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry designAbdelrahman Elshamy0Ahmed Shaker1Yasmine Elogail2Marwa S. Salem3Mona El Sabbagh4Engineering Physics and Mathematics Department, Faculty of Engineering, Ain Shams University, 11517 Cairo, EgyptEngineering Physics and Mathematics Department, Faculty of Engineering, Ain Shams University, 11517 Cairo, Egypt; Corresponding author.Nanotechnology and Nanoelectronics Engineering Department, UST at Zewail City, Giza 12578, EgyptDepartment of Computer Engineering, College of Computer Science and Engineering, University of Ha’il, Ha’il, Saudi Arabia; Department of Electrical Communication and Electronics Systems Engineering, Faculty of Engineering, Modern Science and Arts University (MSA), Cairo, EgyptEngineering Physics and Mathematics Department, Faculty of Engineering, Ain Shams University, 11517 Cairo, EgyptThis study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-channel interface. This technique leads to improved tunneling rates and increased current handling capability. The simulation analysis focuses on optimizing the position and dimension of the high-k dielectric pocket to enhance key device characterization metrics such as ON-state current (ION), ON-to-OFF-state current ratio (ION/IOFF), subthreshold swing (SS), and cutoff frequency (fT). The resulting optimized design for a 30 nm-channel length involves a pocket shift of 1 nm and a pocket length of 12 nm. This configuration achieves a remarkable ON current of 55 µA/µm, which is 30 times higher than that of a conventional TFET. Importantly, other analog performance parameters remain unaffected, with fT surpassing 175 GHz for the 30 nm-channel. Additionally, transient analysis is conducted by applying a resistive load inverter circuit to a pulse input. The fall propagation delay (tphl) exhibits a greater than two orders of magnitude enhancement, along with improved overshoot voltage (VP) compared to a TFET without a pocket. The study further explores the impact of supply scaling on transient parameters. Optimal pocket scalability concerning channel length is found to be 40% for pocket length and approximately 2.5% for pocket shift relative to the source-channel interface. The proposed design significantly enhances DC and analog as well as circuit-level metrics compared to the traditional uniform gate oxide TFET.http://www.sciencedirect.com/science/article/pii/S1110016824001169Hetero-dielectric TFETHigh-K pocketON/OFF current ratioSubthreshold swingCutoff frequencyInverter circuit |
| spellingShingle | Abdelrahman Elshamy Ahmed Shaker Yasmine Elogail Marwa S. Salem Mona El Sabbagh Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design Alexandria Engineering Journal Hetero-dielectric TFET High-K pocket ON/OFF current ratio Subthreshold swing Cutoff frequency Inverter circuit |
| title | Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design |
| title_full | Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design |
| title_fullStr | Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design |
| title_full_unstemmed | Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design |
| title_short | Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design |
| title_sort | performance optimization of high k pocket hetero dielectric tfet using improved geometry design |
| topic | Hetero-dielectric TFET High-K pocket ON/OFF current ratio Subthreshold swing Cutoff frequency Inverter circuit |
| url | http://www.sciencedirect.com/science/article/pii/S1110016824001169 |
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