Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions
Abstract We study a low voltage short pulse operating multilevel memory based on van der Waals heterostack (HS) n-MoSe2/n-MoS2 channel field-effect transistors (FETs). Our HS memory FET exploited the gate voltage (VGS)-induced trapping/de-trapping phenomena for Program/Erase functioning, which was m...
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| Format: | Article |
| Language: | English |
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Nature Portfolio
2022-03-01
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| Series: | npj 2D Materials and Applications |
| Online Access: | https://doi.org/10.1038/s41699-022-00295-8 |
| _version_ | 1811335534774059008 |
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| author | Yeonsu Jeong Han Joo Lee Junkyu Park Sol Lee Hye-Jin Jin Sam Park Hyunmin Cho Sungjae Hong Taewook Kim Kwanpyo Kim Shinhyun Choi Seongil Im |
| author_facet | Yeonsu Jeong Han Joo Lee Junkyu Park Sol Lee Hye-Jin Jin Sam Park Hyunmin Cho Sungjae Hong Taewook Kim Kwanpyo Kim Shinhyun Choi Seongil Im |
| author_sort | Yeonsu Jeong |
| collection | DOAJ |
| description | Abstract We study a low voltage short pulse operating multilevel memory based on van der Waals heterostack (HS) n-MoSe2/n-MoS2 channel field-effect transistors (FETs). Our HS memory FET exploited the gate voltage (VGS)-induced trapping/de-trapping phenomena for Program/Erase functioning, which was maintained for long retention times owing to the existence of heterojunction energy barrier between MoS2 and MoSe2. More interestingly, trapped electron density was incrementally modulated by the magnitude or cycles of a pulsed VGS, enabling the HS device to achieve multilevel long-term memory. For a practical demonstration, five different levels of drain current were visualized with multiscale light emissions after our memory FET was integrated into an organic light-emitting diode pixel circuit. In addition, our device was applied to a synapse-imitating neuromorphic memory in an artificial neural network. We regard our unique HS channel FET to be an interesting and promising electron device undertaking multifunctional operations related to the upcoming fourth industrial revolution era. |
| first_indexed | 2024-04-13T17:25:37Z |
| format | Article |
| id | doaj.art-094c9be2251a4480ac740b684692cad4 |
| institution | Directory Open Access Journal |
| issn | 2397-7132 |
| language | English |
| last_indexed | 2024-04-13T17:25:37Z |
| publishDate | 2022-03-01 |
| publisher | Nature Portfolio |
| record_format | Article |
| series | npj 2D Materials and Applications |
| spelling | doaj.art-094c9be2251a4480ac740b684692cad42022-12-22T02:37:48ZengNature Portfolionpj 2D Materials and Applications2397-71322022-03-01611810.1038/s41699-022-00295-8Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functionsYeonsu Jeong0Han Joo Lee1Junkyu Park2Sol Lee3Hye-Jin Jin4Sam Park5Hyunmin Cho6Sungjae Hong7Taewook Kim8Kwanpyo Kim9Shinhyun Choi10Seongil Im11Van der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityThe school of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST)Van der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityVan der Waals Materials Research Center, Department of Physics, Yonsei UniversityThe school of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST)Van der Waals Materials Research Center, Department of Physics, Yonsei UniversityAbstract We study a low voltage short pulse operating multilevel memory based on van der Waals heterostack (HS) n-MoSe2/n-MoS2 channel field-effect transistors (FETs). Our HS memory FET exploited the gate voltage (VGS)-induced trapping/de-trapping phenomena for Program/Erase functioning, which was maintained for long retention times owing to the existence of heterojunction energy barrier between MoS2 and MoSe2. More interestingly, trapped electron density was incrementally modulated by the magnitude or cycles of a pulsed VGS, enabling the HS device to achieve multilevel long-term memory. For a practical demonstration, five different levels of drain current were visualized with multiscale light emissions after our memory FET was integrated into an organic light-emitting diode pixel circuit. In addition, our device was applied to a synapse-imitating neuromorphic memory in an artificial neural network. We regard our unique HS channel FET to be an interesting and promising electron device undertaking multifunctional operations related to the upcoming fourth industrial revolution era.https://doi.org/10.1038/s41699-022-00295-8 |
| spellingShingle | Yeonsu Jeong Han Joo Lee Junkyu Park Sol Lee Hye-Jin Jin Sam Park Hyunmin Cho Sungjae Hong Taewook Kim Kwanpyo Kim Shinhyun Choi Seongil Im Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions npj 2D Materials and Applications |
| title | Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions |
| title_full | Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions |
| title_fullStr | Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions |
| title_full_unstemmed | Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions |
| title_short | Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions |
| title_sort | engineering mose2 mos2 heterojunction traps in 2d transistors for multilevel memory multiscale display and synaptic functions |
| url | https://doi.org/10.1038/s41699-022-00295-8 |
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