Design and verification of data acquisition clock circuit based on dual-loop phase-locked loop

Background Digital measurement system based on ADCs (analog-to-digital converter) has higher requirement on the signal to noise ratio (SNR) of sampled data. Among all the factors, the jitter of sampling clock has the most prominent effect on SNR. Purpose This study aims to design...

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Bibliographic Details
Main Authors:	LIU Zhi, GAO Guodong, YUE Junhui, CAO Jianshe, DU Yaoyao, MA Huizhou, HE Jun, YE Qiang, TANG Xuhui, LI Yukun, YANG Jing, WEI Shujun
Format:	Article
Language:	zho
Published:	Science Press 2022-10-01
Series:	He jishu
Subjects:	data acquisition dual-loop pll jitter cleaner snr of adc
Online Access:	https://www.hjs.sinap.ac.cn/thesisDetails#10.11889/j.0253-3219.2022.hjs.45.100401&lang=zh

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https://www.hjs.sinap.ac.cn/thesisDetails#10.11889/j.0253-3219.2022.hjs.45.100401&lang=zh

Design and verification of data acquisition clock circuit based on dual-loop phase-locked loop

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