A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of...

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Bibliographic Details
Main Authors: Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
Format: Article
Language:English
Published: IEEE 2017-01-01
Series:IEEE Access
Subjects:
Digital communication
error correction codes
low-density parity check (LDPC) codes
field-programmable gate array
iterative decoding
Online Access:https://ieeexplore.ieee.org/document/7870627/

Internet

https://ieeexplore.ieee.org/document/7870627/

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