A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of...
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| Format: | Article |
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IEEE
2017-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/7870627/ |
| _version_ | 1818558530368569344 |
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| author | Peter Hailes Lei Xu Robert G. Maunder Bashir M. Al-Hashimi Lajos Hanzo |
| author_facet | Peter Hailes Lei Xu Robert G. Maunder Bashir M. Al-Hashimi Lajos Hanzo |
| author_sort | Peter Hailes |
| collection | DOAJ |
| description | Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intrastandard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGAbased LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasicyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance. |
| first_indexed | 2024-12-14T00:13:37Z |
| format | Article |
| id | doaj.art-0ae13a67c73a49b3ae7a4ede8d4d858c |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-14T00:13:37Z |
| publishDate | 2017-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-0ae13a67c73a49b3ae7a4ede8d4d858c2022-12-21T23:25:39ZengIEEEIEEE Access2169-35362017-01-015209652098410.1109/ACCESS.2017.26781037870627A Flexible FPGA-Based Quasi-Cyclic LDPC DecoderPeter Hailes0Lei Xu1Robert G. Maunder2Bashir M. Al-Hashimi3Lajos Hanzo4https://orcid.org/0000-0002-2636-5214School of Electronics and Computer Science, University of Southampton, Southampton, U.K.Programmable Solution Group, Intel Corporation, San Jose, CA, USASchool of Electronics and Computer Science, University of Southampton, Southampton, U.K.School of Electronics and Computer Science, University of Southampton, Southampton, U.K.School of Electronics and Computer Science, University of Southampton, Southampton, U.K.Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intrastandard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGAbased LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasicyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.https://ieeexplore.ieee.org/document/7870627/Digital communicationerror correction codeslow-density parity check (LDPC) codesfield-programmable gate arrayiterative decoding |
| spellingShingle | Peter Hailes Lei Xu Robert G. Maunder Bashir M. Al-Hashimi Lajos Hanzo A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder IEEE Access Digital communication error correction codes low-density parity check (LDPC) codes field-programmable gate array iterative decoding |
| title | A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder |
| title_full | A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder |
| title_fullStr | A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder |
| title_full_unstemmed | A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder |
| title_short | A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder |
| title_sort | flexible fpga based quasi cyclic ldpc decoder |
| topic | Digital communication error correction codes low-density parity check (LDPC) codes field-programmable gate array iterative decoding |
| url | https://ieeexplore.ieee.org/document/7870627/ |
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