Field programmable gate array (FPGA) implementation of novel complex PN-code-generator- based data scrambler and descrambler
A novel technique for the generation of complex and lengthy code sequences using low- length linear feedback shift registers (LFSRs) for data scrambling and descrambling is proposed. The scheme has been implemented using VHSIC hardware description language (VHDL) approach which allows the reconfigur...
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| Format: | Article |
| Language: | English |
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Maejo University
2010-04-01
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| Series: | Maejo International Journal of Science and Technology |
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| Online Access: | http://www.mijst.mju.ac.th/vol4/125-135.pdf |