Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits
Hafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Acce...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-09-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/14/10/1851 |
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| author | Donglin Zhang Honghu Yang Yue Cao Zhongze Han Yixuan Liu Qiqiao Wu Yongkang Han Haijun Jiang Jianguo Yang |
| author_facet | Donglin Zhang Honghu Yang Yue Cao Zhongze Han Yixuan Liu Qiqiao Wu Yongkang Han Haijun Jiang Jianguo Yang |
| author_sort | Donglin Zhang |
| collection | DOAJ |
| description | Hafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Access Memory) still faces challenges related to endurance and retention susceptibility to process variations. Hence, testing and obtaining the core parameters of ferroelectric capacitors continuously is essential to investigate these phenomena and explore the potential solution. The traditional method for measuring ferroelectric capacitors has limitations in timing generation capability, introduces parasitic capacitance, and lacks accuracy for small-area capacitors. In this study, we analyzed the working principle of ferroelectric capacitors and designed a method to detect the remnant polarization, saturation polarization, and imprint offset of ferroelectric capacitors. Further, we further proposed a circuit implementation method. The proposed test circuit conquers these limitations and enables high-precision testing of ferroelectric capacitors, contributing to developing hafnium-based ferroelectric memories. The circuit includes a flip-readout circuit, a capacitance calibration circuit, and a voltage-to-time converter and time-to-digital converter (VTC&TDC) readout circuit. According to simulation results, the capacitance calibration circuit reduces the deviation of the capacitance by 84%, and the accuracy of the readout circuit is 5.91 bits, with a readout time of 150 ns and a power consumption of 1 mW. This circuit enables low-cost acquisition of array-level small-area ferroelectric capacitance data, which can guide subsequent device optimization and circuit design. |
| first_indexed | 2024-03-10T21:02:15Z |
| format | Article |
| id | doaj.art-0c37c7a64f714ae69d9d2de1b3408e64 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T21:02:15Z |
| publishDate | 2023-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-0c37c7a64f714ae69d9d2de1b3408e642023-11-19T17:23:44ZengMDPI AGMicromachines2072-666X2023-09-011410185110.3390/mi14101851Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration CircuitsDonglin Zhang0Honghu Yang1Yue Cao2Zhongze Han3Yixuan Liu4Qiqiao Wu5Yongkang Han6Haijun Jiang7Jianguo Yang8Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaSchool of Microelectronics, University of Science and Technology of China, Hefei 230026, ChinaSchool of Microelectronics, Fudan University, Shanghai 200433, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaSchool of Microelectronics, Fudan University, Shanghai 200433, ChinaSchool of Microelectronics, Fudan University, Shanghai 200433, ChinaZhangjiang Lab, Shanghai 201210, ChinaZhangjiang Lab, Shanghai 201210, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaHafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Access Memory) still faces challenges related to endurance and retention susceptibility to process variations. Hence, testing and obtaining the core parameters of ferroelectric capacitors continuously is essential to investigate these phenomena and explore the potential solution. The traditional method for measuring ferroelectric capacitors has limitations in timing generation capability, introduces parasitic capacitance, and lacks accuracy for small-area capacitors. In this study, we analyzed the working principle of ferroelectric capacitors and designed a method to detect the remnant polarization, saturation polarization, and imprint offset of ferroelectric capacitors. Further, we further proposed a circuit implementation method. The proposed test circuit conquers these limitations and enables high-precision testing of ferroelectric capacitors, contributing to developing hafnium-based ferroelectric memories. The circuit includes a flip-readout circuit, a capacitance calibration circuit, and a voltage-to-time converter and time-to-digital converter (VTC&TDC) readout circuit. According to simulation results, the capacitance calibration circuit reduces the deviation of the capacitance by 84%, and the accuracy of the readout circuit is 5.91 bits, with a readout time of 150 ns and a power consumption of 1 mW. This circuit enables low-cost acquisition of array-level small-area ferroelectric capacitance data, which can guide subsequent device optimization and circuit design.https://www.mdpi.com/2072-666X/14/10/1851ferroelectric capacitorhafniumtest methodologysmall areaarraynon-ideal effect |
| spellingShingle | Donglin Zhang Honghu Yang Yue Cao Zhongze Han Yixuan Liu Qiqiao Wu Yongkang Han Haijun Jiang Jianguo Yang Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits Micromachines ferroelectric capacitor hafnium test methodology small area array non-ideal effect |
| title | Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits |
| title_full | Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits |
| title_fullStr | Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits |
| title_full_unstemmed | Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits |
| title_short | Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits |
| title_sort | methodology for testing key parameters of array level small area hafnium based ferroelectric capacitors using time to digital converter and capacitance calibration circuits |
| topic | ferroelectric capacitor hafnium test methodology small area array non-ideal effect |
| url | https://www.mdpi.com/2072-666X/14/10/1851 |
| work_keys_str_mv | AT donglinzhang methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT honghuyang methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT yuecao methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT zhongzehan methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT yixuanliu methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT qiqiaowu methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT yongkanghan methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT haijunjiang methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits AT jianguoyang methodologyfortestingkeyparametersofarraylevelsmallareahafniumbasedferroelectriccapacitorsusingtimetodigitalconverterandcapacitancecalibrationcircuits |