Reducing the WCET and analysis time of systems with simple lockable instruction caches.
One of the key challenges in real-time systems is the analysis of the memory hierarchy. Many Worst-Case Execution Time (WCET) analysis methods supporting an instruction cache are based on iterative or convergence algorithms, which are rather slow. Our goal in this paper is to reduce the WCET analysi...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Public Library of Science (PLoS)
2020-01-01
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| Series: | PLoS ONE |
| Online Access: | https://doi.org/10.1371/journal.pone.0229980 |