Performance Analysis of Zero Crossing DPLL with Linearized Phase Detector
This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Iran Telecom Research Center
2009-09-01
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| Series: | International Journal of Information and Communication Technology Research |
| Subjects: | |
| Online Access: | http://ijict.itrc.ac.ir/article-1-285-en.html |